The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique which increases the density of integration of input and output buffers in a master slice type semiconductor integrated circuit device. As such, the invention is effective for increasing the number of pins and reducing the size of a chip and further for enhancing the functions of the chip.
A semiconductor integrated circuit device (IC) requires input and output buffers for interfacing with the exterior. As shown in FIG. 1, input or output buffers 4 are disposed and formed between a plurality of bonding pads 2 which are disposed in the peripheral edge of a chip (pellet) 1 and an internal circuit 3 which is disposed in the central area of the chip 1.
In a gate array type or master slice type semiconductor integrated circuit device in which a desired logic circuit can be easily fabricated as the internal circuit by a wiring step, the input and output functions of the bonding pads need to be selected at will in accordance with the design of the internal circuit. To this end, various arrangements are made for the buffers.
FIG. 2 shows an example of one such arrangement. The buffers 4 are provided in correspondence with the bonding pads 2. In each of the buffers 4, circuit elements 5 for constructing the input buffer and circuit elements 6 for constructing the output buffers are formed. In accordance with the design of the internal circuit 3, either the inputting or outputting circuit elements within the buffer 4 are selected and are connected to the bonding pad 2 as well as the internal circuit 3. Thus, the buffer 4 can be constructed as the input or output buffer, and the bonding pad 2 can be constructed as an input terminal or output terminal.
With the above arrangement, however, it is required to form the inputting and outputting circuit elements 5 and 6 in each buffer 4. Therefore, the area occupied by each buffer becomes large. Since the large buffers are arrayed in the peripheral edge of the chip, an increase in the number of the bonding pads 2 (the number of the pins) is limited. On the other hand, when the number of the bonding pads is increased, the chip size enlarges accordingly.
In order to solve this problem, an example in which the number of the bonding pads 2 is approximately double that in the aforementioned example as shown in FIG. 3 has been proposed in Japanese Laid-Open Patent Application No. 57-211248, published Dec. 25, 1982. Both the input buffer and the output buffer can be constructed of one buffer 4, and two bonding pads 2A, 2B are disposed for each buffer. Thus, the input buffer and the output buffer can be connected to the pins and function independently of each other.
The inventor's study, however, has revealed the following. Although the improved arrangement can afford the two functions of inputting and outputting independently of each other by the use of the single buffer, the functions of the respective bonding pads 2A, 2B are limited to inputting (for example, 2A) or outputting (for example, 2B). This leads to problems as stated below. The allotment of the inputting and outputting functions to the respective pads 2 as the signal pins become less versatile, and the versatility of the selection of the functions is diminished. Moreover, although the total number of the pads 2A and 2B increases, the number of the inputting and outputting pads is limited to about 1/2 of the total number mentioned above. In many circuit applications the number of input signals and output signals does not balance, and one is much larger than the other. This is quite common in logic circuits employed in gate array LSIs. In such cases, the resulting substantial number of pads is not greatly different from the number of pads of the foregoing arrangement in FIG. 2 therefore, it is difficult to achieve the purposes of increasing the number of pads, reducing the chip size, etc.